In Chapter 7, we investigate the design of CMOS logic circuits, starting with characterization of the CMOS inverter, and followed by a discussion of the design of NOR,NAND, and complex gates based on a CMOS reference inverter. CMOS gate design is demonstrated to be determined primarily by logic delay considerations. CMOS noise margins and power-delay product are discussed, and the transmission gate is also introduced.

The physical structure of CMOS technology is presented, and parasitic bipolar transistors are shown to exist within the integrated CMOS structure. If these bipolar devices become active, a potentially destructive phenomenon called latchup can occur.