This chapter discussed the structures and i-v characteristics of two types of field-effect transistors (FETs): the metal-oxide-semiconductor FET, or MOSFET, and the junction FET, or JFET.
At the heart of the MOSFET is the MOS capacitor, formed by a metallic gate electrode insulated from the semiconductor by an insulating oxide layer. The potential on the gate controls the carrier concentration in the semiconductor region directly beneath the gate;three regions of operation of the MOS capacitor were identified: accumulation, depletion,and inversion.
A MOSFET is formed when two pn junctions are added to the semiconductor region of the MOS capacitor. The junctions act as the source and drain terminals of the MOS transistor and provide a ready supply of carriers for the channel region of the MOSFET. The source and drain junctions must be kept reverse-biased at all times in order to isolate the channel from the substrate.
MOS transistors can be fabricated with either n- or p-type channel regions and are referred to as NMOS or PMOS transistors, respectively. In addition, MOSFETs can be fabricated as either enhancement-mode or depletion-mode devices.
For an enhancement-mode device, a gate-source voltage exceeding the threshold voltage must be applied to the transistor to establish a conducting channel between source and drain.
In the depletion-mode device, a channel is built into the device during its fabrication, and a voltage must be applied to the transistor's gate to quench conduction.
The JFET uses pn junctions to control the resistance of the conducting channel region. The gate-source voltage modulates the width of the depletion layers surrounding the gate-channel junctions and thereby changes the width of the channel region. A JFET can be fabricated with either n- or p-type channel regions, but because of its structure, the JFETis inherently a depletion-mode device.
Both the MOSFET and JFET are symmetrical devices. The source and drain terminals of the device are actually determined by the voltages applied to the terminals. For a given geometry and set of voltages, the n-channel transistor will conduct two to three times the current of the p-channel device because of the difference between the electron and hole mobilities in the channel.
Although structurally different, the i-v characteristics of MOSFETs and JFETs are very similar, and each type of FET has three regions of operation.
In cutoff, a channel does not exist, and the terminal currents are zero.
In the triode region of operation, the drain current in the FET depends on both the gate-source and drain-source voltages of the transistor. For small values of drain-source voltage, the transistor exhibits an almost linear relationship between its drain current and drain-source voltage. In the triode region, the FET can be used as a voltage-controlled resistor, in which the on-resistance of the transistor is controlledby the gate-source voltage of the transistor. Because of this behavior, the name transistor was developed as a contraction of "transfer resistor."
For values of drain-source voltage exceeding the pinch-off voltage, the drain current of the FET becomes almost independent of the drain-source voltage. In this region, referred to variously as the pinch-off region, the saturation region, or the active region, the drain-source current exhibits a square-law dependence on the voltage applied between the gate and source terminals. Variations in drain-source voltage do cause small changes in drain current in saturation due to channel-length modulation.
Mathematical models for the i-v characteristics of both MOSFETs and JFETs were presented. The MOSFET is actually a four-terminal device and has a threshold voltage that depends on the source-bulk voltage of the transistor.
Key parameters for the MOSFET include the transconductance parameters Kn or Kp, the zero-bias threshold voltage VTO, body effect parameter γ, and channel-length modulation parameter λ as well as the width W and length L of the channel.
The JFET was modeled as a three-terminal device with constant pinch-off voltage. Key parameters for the JFET include saturation current IDSS, pinch-off voltage VP, and channel-length modulation parameter λ.
A variety of examples of bias circuits were presented, and the mathematical model was used to find the quiescent operating point, or Q-point, for various types of MOSFETs. The Q-point represents the dc values of drain current and drain-source voltage: (ID,VDS).
The i-v characteristics are often displayed graphically in the form of either the output characteristics, which plot iD versus vDS, or the transfer characteristics, which graph iD versus vGS. Examples of finding the Q-point using graphical load-line and iterative numerical analyses were discussed. The examples included application of the field-effect transistor as both electronic current and voltage sources.
The most important bias circuit in discrete design is the four-resistor circuit which yields a well-stabilized operating point. On the other hand, the current mirror, in which the output current is a scaled replica of the input current, finds very broad application in the design of both digital and analog integrated circuits. The mirror ratio is controlled by the circuit designer's choice of transistor W/L ratios.
The gate-source, gate-drain, drain-bulk, source-bulk, and gate-bulk capacitances of MOS transistors were discussed, and the Meyer model for the gate-source and gate-bulk capacitances was introduced. All the capacitances are nonlinear functions of the terminal voltages of the transistor. The capacitances of the JFET are determined by the capacitance of the reverse-biased gate-channel junctions and also exhibit a nonlinear dependence on the terminal voltages of the transistor.
Complex models for MOSFETs and JFETs are built into SPICE circuit analysis programs. These models contain many circuit elements and parameters to attempt to model the true behavior of the transistor as closely as possible.
Part of the IC designer's job often includes layout of the transistors based on a set of technology-specific ground rules that define minimum feature dimensions and spaces between features.
Constant electric field scaling provides a framework for proper miniaturization of MOS devices in which the power density remains constant as the transistor density increases. In this case, circuit delay improves directly with the scale factor α, whereas the power-delay product improves with the cube of α.
The cutoff frequency fT of the transistor represents the highest frequency at which the transistor can provide amplification. Cutoff frequency fT improves with the square of the scale factor.
The electric fields in small devices can become very high, and the carrier velocity tends to saturate at fields above 10 kV/cm. Subthreshold leakage current becomes increasingly important as devices are scaled to small dimension.
