Memory organization: In Chapter 8, we have explored basic MOS memory circuits including both random-access memory (RAM) and read-only memory (ROM), sometimes called read-only storage (ROS). The internal organization of IC memories was presented,and examples of the major building blocks of a memory chip, including row and column address decoders, sense amplifiers, word line drivers, and output buffers were investigated.
Static RAM cells: A six-transistor cell is normally used as the storage element in the SRAM, and the integrity of the stored data is maintained as long as power is applied to the circuit.
Dynamic RAM cells: The one-transistor cell is utilized in most high-density dynamic RAM (DRAM) designs. Dynamic memory circuits store the information temporarily as the charge on a capacitor, and the data must be periodically refreshed to prevent loss of the information.Read operations also destroy the data in the cell, and it must be written back into the cell as part of the read cycle. Dynamic memories can also be based on four-transistor dynamic memory cells.
Decoder design: Static NAND and NOR array structures are often utilized in address decoder circuits. Domino CMOS, introduced in Chapter 7, can also be used effectively to reduce power consumption in many applications; a domino CMOS decoder was pre-sented.
Pass transistors: Pass-transistor logic was introduced as one method for simplifying the design of the column decoding circuitry in a RAM.
ROMs: The structure of read only memory or ROM is very similar to that of RAM, but the data is embedded in the physical design of the circuitry.
Register elements: Bistable storage elements based on the cross-coupled inverter pair were introduced including the RS flip-flop, the dynamic D flip-flop or D latch, and the master-slave flip-flop. Flip-flops use the two stable equilibrium points of cross-coupled pair of inverters to represent the binary data. The bistable latch also forms the heart of many sense amplifier circuits, and the unstable equilibrium point of the latch plays a key role in the design of high-speed sensing circuits. Both static and clocked dynamic sense amplifier scan be used in memory designs.
