Chapter 6 introduced a number of concepts and definitions that form a basis for logic gate design.NMOS technology was then used as a vehicle to explore detailed logic circuit design. The geometry of the load device, (W/L)_L, is designed to limit the current and power dissipation of the logic gate to the desired level, whereas the geometry of the switching device, (W/L)_S, is chosen to provide the desired value of V_L. Transistors are usually designed with either W or L set equal to the minimum feature size achievable in a given technology.

• Binary logic states: Binary logic circuits use two voltage levels to represent the Boolean logic variables 1 and 0. In the positive logic convention used throughout this book, the more positive voltage represents a 1, and the more negative level represents a 0. The output of an ideal logic gate would take on only two possible voltage levels: V_H corresponding to the 1 state, and V_L corresponding to the 0 state.
• Logic state transitions: The output of the ideal gate would abruptly change state as the input crossed through a fixed reference voltage V_REF. However, such an abrupt transition cannot be achieved (it requires infinite gain devices). Logic gates implemented with electronic circuits can only approximate this ideal behavior. The transition between states as the input voltage changes is much more gradual, and a precise reference voltage is not defined. V_IL and V_IH are defined by the input voltages at which the slope of the voltage transfer characteristic is equal to -1, and these voltages define the boundaries of the transition region between the logical 1 and 0 levels.
• Noise margins: Noise margins are very important in logic gates and represent a measure of the gate's ability to reject extraneous signals. The high-state and low-state noise margins are defined by NM_H = V_OH - V_IH and NM_L = V_IL - V_OL, respectively. Voltages V_OL and V_OH represent the gate output voltages at the -1 slope points and correspond to the input levels V_IH and V_IL, respectively. The unwanted signals can be voltages or currents coupled into the circuit from adjacent logic gates, from the power distribution network, or by electromagnetic radiation. The noise margins must also absorb manufacturing process tolerance variations and power supply voltage variations.
• Logic design goals: Keep in mind a number of logic gate design goals.
  1. The logic gate should quantize the input signal into two discrete output levels and minimize the width of the undefined input voltage range.
  2. The gate should be unidirectional in nature.
  3. Logic levels must be regenerated as the signal passes through the gate.
  4. Logic gates should have significant fan-in and fan-out capability.
  5. Minimum power and area should be used to meet the speed requirements of the design. Noise margins generally should be as large as possible.
• Logic delays: In the time domain, the transition between logic states cannot occur instantaneously. Capacitances exist in any real circuit and slow down the state transitions, thereby degrading the logic signals. Rise time t_r and fall time t_f characterize the time required for a given signal to change between the 0 and 1 or 1 and 0 states, respectively, and the average propagation delay τ_P characterizes the time required for the output of a given gate to respond to changes in its input signals. The propagation delays on the high-to-low (τ_PHL)and low-to-high (τ_PLH) transitions are typically not equal, and τ_P is equal to the average of these two values.
• Power-delay product: The power-delay product PDP, expressed in picojoules (pJ) or fem-tojoules (fJ), is an important figure of merit for comparing logic families. At low power levels, the power-delay product is a constant, and the propagation delay of a given logic family decreases as power is increased. At intermediate power levels, the propagation delay becomes independent of power level, and at high power levels, the propagation delay of bipolar logic families actually degrades as power is increased.
• Boolean algebra: Boolean algebra, developed by G. Boole in the mid-1800s, is a powerful mathematical tool for manipulating binary logic expressions. Basic logic gates provide some combination of the NOT, AND, OR, NAND, or NOR logic functions. A complete logic family must provide at least the NOT function and either the AND or OR functions.
• Diode and DTL logic: Simple AND and OR gates can be constructed using diodes, but a transistor must be added to achieve the inversion operation. The combination of a diode AND gate and a bipolar transistor forms a DTL NAND gate.
• NMOS inverter with resistor load: Basic inverter design was introduced by considering the static behavior of an inverter using an NMOS switching transistor and a resistor load. Although simple in concept, the resistor is not feasible for use as a load element in ICs because it consumes too much area.
• IC inverters: In integrated circuits, the resistor load in the logic gate is replaced with a second MOS transistor, and three possibilities were investigated in detail: the saturated load device, the linear load device, and the depletion-mode load device.
• Saturated load: The saturated load device is the most economical configuration because it does not require any modification to the basic MOS fabrication process. However, saturated load circuits offer the poorest performance in terms of propagation delay.
• Linear load: The linear load configuration offers improved performance but requires an additional power supply voltage, which is both expensive and causes substantial wiring congestion in ICs.
• Depletion-mode load: Depletion-mode load circuits require additional processing in order to create MOSFETs with a second value to threshold voltage. However, substantial performance improvement can be obtained, and NMOS depletion-mode load technology waste workhorse of the microprocessor industry for many years.
• NOR and NAND gates: Multi-input NOR and NAND gates can both easily be implemented in MOS logic. The NOR gate is formed by placing additional transistors in parallel with the switching transistor of the basic inverter, whereas the NAND gate is formed by several switching devices connected in series.
• Complex logic gates: An advantage of MOS logic is its ability to implement complex sum-of-products and product-of sums logic equations in a single logic gate, by utilizing both parallel and series connections of the switching transistors. A single load device is required for each logic gate, and one switching transistor is required for each logic input variable.
• Reference inverter based design: Once the reference inverter for a logic family is designed, NAND, NOR, and complex gates can all be designed by applying simple scaling rules to the geometry of the reference inverter.
• MOS body effect: The influence of the MOSFET body effect cannot be avoided in integrated circuits, and it plays an important role in the design of NMOS (or PMOS) logic gates. Body effect reduces the value of V_H in saturated load logic and generally degrades the current delivery capability of all the load device configurations, thereby increasing the delay of all the logic gates. The MOS body effect has a minor influence on the design of the W/L ratios of the switching transistors in complex logic gates.
• Rise time, fall time, and propagation delay: Equations were developed for the rise time, fall time, and propagation delays of the various types of NMOS logic gates, and it was shown that all the time delays of MOS logic circuits are directly proportional to the total equivalent capacitance connected to the output node of the gate. The total effective ca-pacitance is a complicated function of operating point and is due to the capacitance of the interconnections between gates as well as the capacitances of the MOS devices, which include the gate-source (C_GS), gate-drain (C_GD), drain-bulk (C_DB), and source-bulk (C_SB) capacitances.
• Static and dynamic power dissipation: Power dissipation of a logic gate has a static component and a dynamic component. Dynamic power dissipation is proportional to the switching frequency of the logic gate, the total capacitance, and the square of the logic voltage swing. At low switching frequencies, static power dissipation is most important, but at high switching rates the dynamic component becomes dominant. For a given load capacitance, the power and speed of a logic gate can be changed by pro-portionately scaling the geometry of the load and switching transistors. For example,doubling the W/L ratios of all devices doubles the power of the gate without chang-ing the static voltage levels of the design. This behavior is characteristic of "ratioed" MOSlogic.
• PMOS logic: PMOS logic gates are mirror images of the NMOS gates. In order to equal the performance of NMOS, the size of the transistors must be increased in order to compensate for the lower mobility of holes compared to electrons.