CMOS inverters: In this chapter, we discussed the design of CMOS logic circuits beginning with the design of a reference inverter. The shape of the voltage transfer characteristic (VTC)of the CMOS inverter is almost independent of power supply voltage, and the noise margins of a symmetrical inverter can approach one-half the power supply voltage. The design of the W/L ratios of the transistors in a CMOS gate is determined primarily by the desired propagation delay τP, which is related directly to the device parameters K'n, VTN, K'p, VTP and the total load capacitance C.
CMOS logic gates: In CMOS logic, each gate contains both an NMOS and a PMOS switching network, and every logical input is connected to at least one NMOS and one PMOStransistor. NAND gates, NOR gates, and complex CMOS logic gates can all be designed using the reference inverter concept, similar to that introduced in Chapter 6. As for NMOS circuitry, complex CMOS gates can directly implement Boolean logic equations expressed in a sum-of-products form. In contrast to NMOS logic, which has highly asymmetric rise and fall times, symmetrical inverters in which tf and tr are equal can easily be designed in CMOS, although there can be a significant area penalty. A number of examples of styles for the layout of CMOS inverters and more complex logic gates were presented.
Body effect: Body effect has a smaller influence on CMOS design than on NMOS design because the source-bulk voltages of all the transistors in a CMOS gate become zero in the steady state. However, the source-bulk voltages are nonzero during switching transients,and the body effect degrades the rise and fall times and propagation delays of CMOS logic.
Dynamic power dissipation and power delay product: Except for very low power applications, CMOS power dissipation is determined by the energy required to charge and discharge the effective load capacitance at the desired switching frequency. A simple ex-pression for the power-delay product of CMOS was developed. For a given capacitive load,the power and delay of the CMOS gate may be scaled up or down by simply modifying the W/L ratios of the NMOS and PMOS transistors.
Static power dissipation: For low-power applications, particularly where battery life is important, leakage current from the reverse-biased wells and drain-substrate junctions can become an important source of power dissipation. This leakage current actually places a lower bound on the power required to operate a CMOS circuit.
"Short circuit" current: During switching of the CMOS logic gate, a pulse of current occurs between the positive and negative power supplies. This current causes an additional component of power dissipation in the CMOS gate that can be as much as 20 to 30 percent of the dissipation resulting from charging and discharging the load capacitance.
Cascade buffers: High capacitance loads are often encountered in logic design, and cascade buffers are used to minimize the propagation delay associated with driving these large capacitance values. Cascade buffers are widely used in word line drivers and for on-chip and off-chip bus driver applications.
Dynamic logic: Dynamic logic circuits, such as domino CMOS, operate on two phases -- a precharge phase and a logic evaluation phase. This circuit family requires only a single PMOS transistor in each gate (plus an output inverter), thus reducing the large silicon area overhead traditionally associated with static CMOS logic circuits. Dynamic circuits are also used to reduce power consumption in many applications.
The CMOS transmission gate: A new bidirectional circuit element, the CMOS transmission gate that utilizes the parallel connection of an NMOS and a PMOS transistor was introduced.When the transmission gate is on, it provides a low-resistance connection between its input and output terminals over the entire input voltage range. We often find the transmission gate used in circuit implementations of both the D latch and the master-slave D flip-flop. (See Chapter 8).
Latchup: An important potential failure mechanism in CMOS is the phenomenon called latchup, which is caused by the existence of parasitic npn and pnp bipolar transistors in the CMOS structure. A lumped circuit model for latchup was developed and used to simulate the latchup behavior of a CMOS inverter. Special substrates and IC processing are used to minimize the possibility of latchup in modern CMOS technologies.
